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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6728B/D 256K x 4 Bit Fast Static Random Access Memory The MCM6728B is a 1,048,576 bit static random access memory organized as 262,144 words of 4 bits. This device is fabricated using high performance silicon-gate BiCMOS technology. Static design eliminates the need for external clocks or timing strobes. This device meets JEDEC standards for functionality and revolutionary pinout, and is available in a 400 mil plastic small-outline J-leaded package. * * * * * * Single 5 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: 8, 10, 12 ns Center Power and I/O Pins for Reduced Noise MCM6728B WJ PACKAGE 400 MIL SOJ CASE 810-03 PIN ASSIGNMENT A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A A A A A DQ3 VSS VCC DQ2 A A A A A BLOCK DIAGRAM A A A A A A A A A DQ0 INPUT DATA CONTROL DQ3 A A COLUMN I/O COLUMN DECODER ROW DECODER MEMORY MATRIX 512 ROWS x 512 x 4 COLUMNS VCC VSS A E DQ0 VCC VSS DQ1 W A A A A PIN NAMES A0 - A17 . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . Write Enable DQ0 - DQ3 . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . No Connection A A A A A A A E W REV 2 5/95 (c) Motorola, Inc. 1995 MOTOROLA FAST SRAM MCM6728B 1 TRUTH TABLE (X = Don't Care) E H L L W X H L Mode Not Selected Read Write VCC Current ISB1, ISB2 ICCA ICCA Output High-Z Dout High-Z Cycle -- Read Cycle Write Cycle ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 1.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature--Plastic Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5 VCC + 0.3** 0.8 Unit V V V * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 2.0 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 2.0 ns) for I 20.0 mA. DC CHARACTERISTICS Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V POWER SUPPLY CURRENTS Parameter AC Active Supply Current (Iout = 0 mA) (VCC = max, f = fmax) Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) AC Standby Current (E = VIH, VCC = max, f = fmax) CMOS Standby Current (VCC = max, f = 0 MHz, E VCC - 0.2 V, Vin VSS + 0.2 V, or VCC - 0.2 V) Symbol ICCA ICC2 ISB1 ISB2 6728B-8 195 90 60 20 6728B-10 165 90 60 20 6728B-12 155 90 60 20 Unit mA mA mA mA 1, 2, 3 Notes 1, 2, 3 NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero. MCM6728B 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested) Parameter Address Input Capacitance Control Pin Input Capacitance Input/Output Capacitance Symbol Cin Cin CI/O Typ -- -- -- Max 6 6 8 Unit pF pF pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A READ CYCLE TIMING (See Notes 1 and 2) 6728B-8 Parameter Read Cycle Time Address Access Time Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tAXQX tELQX tEHQZ Min 8 -- -- 3 3 0 Max -- 8 8 -- -- 4 6728B-10 Min 10 -- -- 3 3 0 Max -- 10 10 -- -- 5 6728B-12 Min 12 -- -- 3 3 0 Max -- 12 12 -- -- 6 Unit ns ns ns ns ns ns 4,5,6 4,5,6 Notes 3 NOTES: 1. W is high for read cycle. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max < tELQX min, for a given device. 5. Transition is measured 200 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL). 8. Addresses valid prior to or coincident with E going low. AC TEST LOADS +5 V OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF 480 TIMING LIMITS The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1A Figure 1B MOTOROLA FAST SRAM MCM6728B 3 READ CYCLE 1 (See Note 7) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID READ CYCLE 2 (See Note 8) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX Q (DATA OUT) tAVQV DATA VALID tEHQZ MCM6728B 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6728B-8 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 8 0 8 8 4 0 0 3 0 Max -- -- -- -- -- -- 4 -- -- 6728B-10 Min 10 0 9 9 5 0 0 3 0 Max -- -- -- -- -- -- 5 -- -- 6728B-12 Min 12 0 10 10 6 0 0 3 0 Max -- -- -- -- -- -- 6 -- -- Unit ns ns ns ns ns ns ns ns ns 4,5,6 4,5,6 Notes 3 NOTES: 1. A write occurs during the overlap of E low and W low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady-state voltage with load of Figure 1B. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. WRITE CYCLE 1 tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWHQX tDVWH DATA VALID tWHDX tWHAX MOTOROLA FAST SRAM MCM6728B 5 WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) 6728B-8 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 8 0 7 7 4 0 0 Max -- -- -- -- -- -- -- 6728B-10 Min 10 0 8 8 5 0 0 Max -- -- -- -- -- -- -- 6728B-12 Min 12 0 9 9 6 0 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 4,5 Notes 3 NOTES: 1. A write occurs during the overlap of E low and W low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX tELWH tEHAX Q (DATA OUT) HIGH-Z MCM6728B 6 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 28-LEAD 400 MIL SOJ CASE 810-03 F N DETAIL Z D 28 PL 0.18 (0.007) 14 28 15 1 M TA S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810-01 AND -02 OBSOLETE, NEW STANDARD 810-03. MILLIMETERS MIN MAX 18.29 18.54 10.04 10.28 3.26 3.75 0.39 0.50 2.24 2.48 0.67 0.81 1.27 BSC -- 0.50 0.89 1.14 0.64 BSC 5 0 0.76 1.14 11.05 11.30 9.15 9.65 0.77 1.01 INCHES MIN MAX 0.720 0.730 0.395 0.405 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC -- 0.020 0.035 0.045 0.025 BSC 0 5 0.030 0.045 0.435 0.445 0.360 0.380 0.030 0.040 H BRK -AL G M M E 0.10 (0.004) K DETAIL Z -TSEATING PLANE 0.18 (0.007) P S TB S -BC R 0.25 (0.010) S S RAD TB S DIM A B C D E F G H K L M N P R S ORDERING INFORMATION (Order by Full Part Number) MCM 6728B WJ Motorola Memory Prefix Part Number XX X Shipping Method (R = Tape and Reel, Blank = Rails) Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns) Package (WJ = 400 mil SOJ) Full Part Numbers -- MCM6728BWJ8 MCM6728BWJ8R MCM6728BWJ10 MCM6728BWJ10R MCM6728BWJ12 MCM6728BWJ12R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA FAST SRAM MCM6728B 7 Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM6728B 8 *MCM6728B/D* MCM6728B/D MOTOROLA FAST SRAM |
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